1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to semiconductor structures wherein integrated circuits are stacked on top of each other to allow vertically integrated circuits.
2. Description of the Related Art
Throughout the evolution of integrated circuits, it has been realized that the need for improvements can be focused on two items: (1) increasing the functional complexity of the circuits, whereby the device area should decrease; and (2) increasing the circuit speed, allowing an overall improvement of the circuit performance. With regard to the increase in functional complexity, this results mainly in an increase in functional density, while at the same time the shrinking size of chip structures is also of importance. The functional density, which is of primary importance, is defined as the number of interconnected devices per chip area. In contrast to this, the number of devices per chip area is referred to as the device density.
Improvements in the technology of integrated circuits steadily allow an increasing device density. However, the area which is occupied by the interconnection lines between the on-chip devices grew more quickly, as exemplified below, such that the condition was reached in which the functional density, and therefore the chip area, became interconnect-limited. This means that the shrinking of device structures does not lead to an increase in functional density, and would, therefore, not lead to an improved circuit performance. The following simplified example illustrates the limitation of the functional density due to device interconnections.
Assuming that five devices have to be completely interconnected with each other, such that every device is connected to each and every other device, in this case ten interconnection lines are required. Further assuming that the five devices occupy the same area as the interconnection lines, the interconnection lines will consequently occupy half (50%) of the total chip area.
When looking at a second case where ten devices should be interconnected, a complete interconnection between each of the devices, such that every device is connected to each and every other device, would require 45 connection lines. This means that when the area of the devices is doubled, the area of the connection lines increases by a factor of 4.5, provided that every connecting line has the same length. While in the first case the area of the interconnection lines occupies half of the chip area, in the latter case it occupies approximately two-thirds of the chip area.
As a result, with increasing device density, the share in total area of the area occupied by interconnection lines increases. For example, in Proceedings of the IEEE, Vol. 69, p. 267, 1981, a report on a case of a bipolar chip comprising 1,500 gates fabricated on a chip area of 0.29 cm2 using single level metal (horizontal interconnection) with a pitch of 6.5 μm cited the total area of the connection wires as 0.26 cm2, which is approximately nine-tenths of the surface area of the chip. Consequently, there exists a limitation point where an additional device element would require as much additional area of interconnection lines that the functional density would decrease although the structure size decreases.
One approach to overcome this limitation due to the complexity of the interconnection between devices on one chip level is to introduce multi-level interconnect technology, whereby more than one circuit level is interconnected vertically such that the complexity in one level can be reduced.
With regard to improvement in circuit performance by increasing circuit speed, there are also limitations due to the switching speed of MOS transistors and the propagation delay in the interconnect wires. At the currently used device dimensions, however, the switching speed of the MOS transistor itself does not limit the logic delay of the integrated circuit (IC). In other words, as the devices shrink, the device contribution to the propagation delay also decreases. Scaling down interconnection line widths, however, necessarily increases the propagation delay time due to the increasing resistance and parasitic capacitance. Since the propagation delay time is further influenced by the interconnection path length, and since the interconnection path lengths also increase with the functional density, the circuit speed becomes interconnect propagation delay time-limited.
In view of this, an interconnecting technology between different levels would allow reduction of interconnection complexity in one level and would, therefore, increase the functional density. The length of connecting lines within one level, as well as optimization of the rooting of the interconnect lines, would reduce parasitic capacitance, resistance and signal cross-talk. This results in an overall increase in the system speed.
A multi-layered structure with vertical interconnections is described, for example, in U.S. Pat. No. 5,793,115. Each circuit layer described in this patent can be fabricated in a separate wafer or thin film material and subsequently transferred onto the layered structure and interconnected. In particular, this document describes a microprocessor divided into functional blocks, for instance an arithmetic logic unit (ALU), a controller, memory elements, etc., which are fabricated in the same or separate semiconductor wafers and then stacked. Typically, the functional blocks communicate with one another using address, data and control buses. These buses consist of a number of metal wires that are routed along the surface of a silicon chip. Typically, the metal wires run in areas of the chip between the functional blocks and take up a considerable amount of real estate, as much as half of that available. The functional blocks of the circuit are divided into two or more sections with one section of the circuit on a bulk chip and the remaining blocks on an overlaying thin film with components electrically connected through an intervening insulating layer. The circuits may be formed in silicon on insulator (SOI) structures and are mounted together by using epoxy. Interconnections are formed with an epoxy which is electrically and thermally conductive.
However, the two wafers are combined via an epoxy layer, which has disadvantages with regard to electrical insulation and stability compared to insulation materials like silicon dioxide. Moreover, the contact vias are filled with an electrically and thermally conductive epoxy, exhibiting poorer conductivity compared to a metallic connection. Consequently, only a low aspect ratio (depth/width) of the contact vias can be achieved.
Another approach to achieve a vertical integration is described by Ruth DeJule in Semiconductor International in November 1999. There, a three-dimensional SOI structure using epitaxial lateral overgrowth is described. In this process, layers of silicon on insulator are created by forming oxide wells, thermally grown to a thickness of about 300 nm, followed by a lithography step to define islands. The oxide is etched by reactive ion etching. Using low pressure chemical vapor deposition (LPCVD), silicon epitaxial layers are grown selectively (selective epitaxial growth, SEG), seeded through oxide windows that pick up the atomic template from a substrate or from an SOI island on a preceding layer. At the top edge of the window, growth continues laterally, filling adjacent recessed wells to a maximum distance of 20-50 μm at growth rates of 0.11 μm/minute. The location of the SEG windows, whereby the distance therebetween is as narrow as 200 nm, is defined lithographically.
The disadvantage of this process is that each preceding layer is exposed to the process conditions of the currently processed layer. This means that for the formation of a device with stacked layers, a completely new process scheme has to be developed which carefully avoids the interference of process steps with underlying layers. Typically, corresponding processes may not be compatible with any established process in a chip plant and are, therefore, extremely cost-intensive.
Although the state of the art teaches processes for vertical integration, it is desirable to provide a process for stacking and interconnecting silicon on insulating layers leading to more reliable vertical integrated circuits, thereby only necessitating a minimum of process steps for fusing and interconnecting the silicon on insulator layers, whereby the influence of this process on the already processed circuits in the silicon on insulator films is minimized.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.